Capacitor constructions continue to have increasing aspect ratios in higher generation integrated circuitry fabrication. For example, dynamic random access memory (DRAM) capacitors may have elevations of from 2 to 3 microns, with widths of about 0.1 micron.
It is a continuing goal to increase the density of semiconductor devices, with a corresponding goal to reduce the footprint associated with individual devices. As the packing density of capacitor devices becomes increasingly greater, the available surface area for capacitance decreases. Accordingly, capacitors are being formed to be increasingly tall and thin.
Two types of common capacitor constructions are so-called container-type devices, and so-called stud-type devices. Container-type devices have a storage node electrode shaped as a container, and stud-type devices have a storage node electrode shaped as a solid pedestal. Container-type devices have an advantage over stud-type devices of providing more capacitive area in a given space, but may be structurally weak compared to stud-type devices.
Regardless of whether the capacitor constructions are stud-type devices or container-type devices, the capacitor constructions may become prone to toppling and/or breaking from an underlying base as the capacitor constructions become increasingly tall and thin.
A method which has been developed to provide support to tall, thin capacitors is to utilize a lattice structure to support the capacitors. U.S. Pat. Nos. 7,226,845 and 7,387,939 describe example lattice structures. Unfortunately, the ever-increasing aspect ratio requirements of capacitors are pushing the height-to-width ratios of the capacitors to levels that are difficult to achieve, even utilizing the lattice structures for support.
It would be desirable to develop new methods of forming and supporting high-aspect-ratio capacitor constructions; and to develop new capacitor constructions that can be formed to high aspect ratios.